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nextnano3 - Tutorialnext generation 3D nano device simulator1D Tutorialp-Si / SiO2 / poly-Si structure (MOSFET with inversion channel due to applied gate voltage)Note: This tutorial's copyright is owned by Stefan Birner, www.nextnano.de. Authors:
Stefan Birner If you want to obtain the input file that is used within this tutorial, please contact stefan.birner@nextnano.de.
p-Si / SiO2 / poly-Si structure (MOSFET with inversion channel due to applied gate voltage)
Step 1: Layer sequence
The applied gate voltage leads to confined electron states at the p-Si / SiO2
interface (n-type inversion layer) whereas the holes are repelled from
the Si/SiO2 surface towards the interior of the device (i.e. to the
left side).
Step 2: CalculationsThe temperature was set to 300 Kelvin. Self-consistent solution of the 1D-Schrödinger-Poisson equation within single-band effective-mass approximation (using ellipsoidal effective mass tensors) for the (Delta) conduction band edges. We vary the gate voltage from 0 V to 2.7 V in steps of 0.1 eV.
Step 3: Results
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